The Neuromorphics Project aims to build Brainstorm, a million-neuron neuromorphic chip tailored to run whole-brain models.
In particular, the five-year goal of this ONR-funded project, which began in April 2013, is to build a multichip neuromorphic system that will run Spaun in real-time while consuming milliwatts of power. This whole-brain model’s 2.3M-neuron network was synthesized automatically from a specification of population-level representations and transformations. This automatic synthesis method, known as the Neural Engineering Framework (NEF), made it possible to achieve unprecedented network scale—Spaun is the largest behaving brain model.
Spaun demonstrates that automatically synthesized spiking-neuron networks can accomplish visual, cognitive, and motor tasks. It performs a total of eight different cognitive visuomotor tasks autonomously with a network of 2,341,242 spiking-neurons organized into 32,143 layers connected by 896,205,908 synapses. For example, its 220K-neuron visual hierarchy recognizes handwritten digits (MNIST database) presented to its 28×28 pixel retina. Its 1M-neuron dorsolateral prefrontal cortex keeps track of the sequence of digits it has seen. Its 500K-neuron ventrolateral prefrontal cortex predicts the next digit in a sequence. And its 35K-neuron motor cortex controls its arm to write down the digit it predicted. Currently, simulating one second of Spaun’s behavior takes 2.5 hours on a sixteen-core PC—nine-thousand times slower than real-time.
Brainstorm is the first chip to be designed specifically to implement spiking neural networks that are synthesized from a high-level description. Starting with a desired mathematical computation, NEF defines an encoding between each variable in the computation and the pattern of spiking activity in a layer of neurons. It then derives layer-to-layer synaptic weights that transform one spike-activity pattern into another so as to implement the desired computation. If neurons are akin to logic gates and synaptic connections are akin to wiring between these gates, then NEF is akin to the tool that synthesizes the circuit’s netlist, wiring the gates together, given a Verilog description.